In the effort to realize high-speed and performance data processing systems, there has been, based on electronic device innovation and specifically on submicron technology, a surge in the development of microstructure devices that take advantage of the high speed property of electrons in GaAs. A number of transistor types have been built. The most commercially successful of these devices is the MESFET--both the depletion mode (or D-MESFET) and enhancement mode (or E-MESFET) types. Under the gate of a D-MESFET is a normally-on region depleted of electrons which allows current to pass between the source and drain of the transistor. This region is doped to be n-type. When a negative voltage is applied, the width of the depletion region increases, the channel width through which the current flows decreases and the current flow is eventually pinched off. In an E-MESFET, the region under the gate is doped so that the channel is normally pinched off. Thus, small positive gate bias voltage must be applied for current to flow between the source and drain.
To meet the demands of higher speed and integration density, the MESFET needs continual improvement. Potential improvements include shortening of the gate length, reducing the series resistance between the source and gate, decreasing the parasitic capacitances, especially the gate-source and gate-drain overlap capacitances, rendering the source/drain junction depths small and providing contact metallurgy which has a low resistivity and high thermal stability and compatible with shallow junctions.
In this connection, the publication by K. Ueno et al entitled "High Transconductance GaAs MESFET with Reduced Short Channel Effect Characteristics" IEDM 85, pages 82-85 (1985) describes a GaAs MESFET, wherein the gate formed by etching a WSi.sub.x film. This publication discloses reducing short channel effect by employing a highly doped channel layer grown by molecular beam epitaxy and minimizing parasitic capacitance by utilizing oxide sidewall spacers between the gate and source/drain. Ueno et al uses a hot gate process in which the gate is formed first, followed by the formation of the source/drain. The basic disadvantage of the hot gate process is that the gate metal (WSi.sub.x) has a high resistivity which is not desirable for interconnection purposes. Also, the hot gate process does not permit threshold voltage trimming late in the device fabrication.
The publication by K. Osaiune et al entitled "Above 10 GHz Frequency Dividers with GaAs Advanced Saint and Air-bridge Technology", Electronics Letters, Vol. 22, page 69 (1986) discloses a flat-gate MESFET having a reduced gate overlap parasitic capacitance. The gate is formed from a dual layer of Mo and Au. After forming the gate by ion-milling planarization process, source/drain ohmic contacts are formed by AuGe/Ni deposition and sintering. The basic shortcoming of this disclosure is that it is unsuitable for forming submicron sized MESFET owing to significant (as much as 0.5 micron) lateral migration at high temperature of the gold in the AuGe/Ni metallurgy used for source/drain contacts causing electrical shorting. Also, the vertical transport of the gold precludes use of this process for forming shallow junction devices. Importantly, this process is limited to fabrication of a MESFET having a gate width dictated by resolution limit of lithography.
The invention overcomes these and other problems of the prior art by means of a novel MESFET structure and a novel cold gate process for its fabrication.